architecture
Native Code Generation
From LLVM IR to optimised machine code for your CPU.
Published May 30, 2026
Instruction Selection
LLVM maps IR instructions to target CPU instructions.
Register Allocation
Variables are assigned to CPU registers where possible.
Instruction Scheduling
Instructions are reordered to maximise pipeline utilisation.
Vectorisation
At opt_level 3, LLVM may auto-vectorise loops using SIMD.